CPU_RST and VDD_FLASH
I have some issues with my Omega2S+ on a custom board. The CPU does not reboot after reset, and this HW reset circuit has been implemented.
I notice that even with Q2 (in the diagram of topic 2927) shut off (or even removed from the PCB) there is around 2V on the VDD_FLASH pin. I assume this is enough to keep the flash from resetting to 3 byte mode.
Does anyone know how to make sure the reset works?
Re: Omega2S Reset Pin C21 shutdown instead of reset
I notice that even with Q2 (in the diagram of topic 2927) shut off (or even removed from the PCB) there is around 2V on the VDD_FLASH pin.
Probanly you have applied Option 1
*and Option 2 simultaneously on your custom board.
*or there's some similar connection between VCC33 and VDD__FLASH)
Please check your custom PCB.
Omega2S-Reference-Schematic.pdf (That Q2 is Q1 here. ;)
I don't see why that would be making a lot of change, but I implemented an additional FET which shorts VDD_FLASH to ground when reset is active. Gate is connected to the drain of Q2.
It's not a solution that makes me proud, but it works.