@György-Farkas The + versions have 32 mbyte flash, which cannot be addressed in 3 byte mode. The power on reset for the flash is 3 byte mode, after boot they are switched to 4 byte address mode.
I only have experience with the + versions. I do not know if the normal versions use 3 or 4 byte addressing mode.
@Jeff-Seese Omega2s will reset, but won't be able to boot because the flash chip is still configured in 4 byte mode while the omega expects 3 byte mode after reset. You need to reset the omega2s and the flash together.
@Arek-Z I modified the bootloader on an omega2s+, based on the github repo of onion. This went fine without problems. For flashing, I use a FTDI SPI cable in combination with the most recent version of flashrom, which works out of the box. You can freely write the flash as long as you keep the processor in reset, so unbricking is not a problem and all required HW signals are available on the omega2s. Just make sure that you don't erase the second partition, I don't think you can restore that one.
In practical terms, I added a programming header that contains the SPI signals as well as ground, 3V3 and reset. When the programming header is inserted, a short keeps the processor in reset, so that the flash can be safely programmed. This method only works with the s/s+ version of the omega.
Make your own PCB, and only put the things on it that you need. For many projects the omega2s takes care of the mandatory risky stuff (like the high-speed SDRAM interface). It's not hard to find 5$/10 prototype PCB services these days, which means that shipping is more expensive that making a PCB.
Omega2s is more interesting if you want to have your boards produced in large quantities, since it can be automatically pick-and-placed.
@luz I have only seen data corruption in full duplex mode, half duplex works. It would surprise me if half duplex mode has a bug, since the SPI flash works reliable. In full duplex, I have observed errors in the second bit (always 1 or 0, don't remember exactly), depending on the state of the first bit. This makes the first transmitted byte unreliable.
@cas sorry, time does not permit that now. I did not install extra packages or feeds apart from what I described above. On the other hand, I made quite some changes to the spi driver, dts files, ... which may or may not have an impact on the good operation of the WiFi driver.
@cas we have not seen that problem. WiFi seems to work as good as with Omega's original firmware.
@Shreyansh-Jain, to add the WiFi drivers, I first did 'scripts/feeds update', then 'script/feeds install ralink-wifi-mt76x8', then in 'make menuconfig' select the Ralink APSoC wifi driver in Onion->Ralink, and then build.
I've also made some minor modifications to the SPI driver:
In general, I mainly threw code out to rely more on the generic spi.c infrastructure. Together with some modifications to the .dts file, this resolves many of the issues that people complain about on the SPI driver. Additionally, the driver can now support 'fast read' and does not need the chunked-io parameter. This speeds up in general performance of flash accesses. Combined with a higher SPI clock speed, I have obtained more than double of the flash read performance compared to the current driver.
Example modifications to the dts file:
For CS GPIOs:
cs-gpios = <0>, <0>, <&gpio1 9 0>, <&gpio1 10 0>;
...
spidev@2 {
compatible = "spidev";
reg = <2>;
spi-max-frequency = <40000000>;
};
spidev@3 {
compatible = "spidev";
reg = <3>;
spi-max-frequency = <40000000>;
};
For better flash performance:
- m25p,chunked-io = <31>;
+ m25p,fast-read;
I've put the driver on github https://github.com/wdu/mt7688
@sza2-sza2 Your analysis is correct, the problem affects pin 14 through 29, and is easily fixed is in the bootloader:
diff --git a/drivers/rt2880_eth.c b/drivers/rt2880_eth.c
index 7c83a46..9b6f1ec 100644
--- a/drivers/rt2880_eth.c
+++ b/drivers/rt2880_eth.c
@@ -2134,6 +2134,8 @@ void rt305x_esw_init(void)
/*TODO: Init MT7628 ASIC PHY HERE*/
i = RALINK_REG(RT2880_AGPIOCFG_REG);
i = i & ~(MT7628_EPHY_EN);
+ // only enable PHY 0
+ i = i | (0x1e << 16);
RALINK_REG(RT2880_AGPIOCFG_REG) = i;
printf("Resetting MT7628 PHY.\n");