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Omega2S+/2+: Software solution to the problem of a broken watchdog



  • Hi,

    Without going into details. I don't know if you know, but the hardware watchdog never worked in Omega2S+/2+. This was a disqualifying problem for me.

    I am enclosing a patch that fixes this problem.

    Have a nice day

    --- a/drivers/mtd/spi-nor/spi-nor.c
    +++ b/drivers/mtd/spi-nor/spi-nor.c
    @@ -1086,7 +1086,7 @@
     	{ "mx25u6435f",  INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
     	{ "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
     	{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
    -	{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
    +	{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
     	{ "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
     	{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
     	{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
    


  • How does SPI flash driver affect watchdog?



  • @user5456

    • By default both the Omega2+ CPU and Flash memory boots from a 3 Byte address mode
    • During boot loader the CPU upgrades both Flash memory and itself to a 4 Byte address mode in order to access higher memory addresses
    • During an unexpected reset (brownout) the CPU resets but the memory remains in the 4 Byte address mode.
    • The mismatch in the address mode prevent the CPU from booting normally.


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